# Active Challenge
Source: https://docs.chipforge.io/api-reference/endpoint/active
POST /plants
/active
Get currently available challenges
# Check Submission
Source: https://docs.chipforge.io/api-reference/endpoint/check
/status
Track evaluation progress and retrieve scores
# Current Batch
Source: https://docs.chipforge.io/api-reference/endpoint/current
/batch/current
Retrieve current submission batch for evaluation
# Generate submissions id
Source: https://docs.chipforge.io/api-reference/endpoint/generate
GET /plants
/generate-submission-id
for solution submission
# Challenge Info
Source: https://docs.chipforge.io/api-reference/endpoint/info
DELETE /plants/{id}
/info
Retrieve challenge details, time remaining, and file locations
# Submit Score
Source: https://docs.chipforge.io/api-reference/endpoint/score
/submit_score
Submit evaluation results with comprehensive metrics
# Submit Solution
Source: https://docs.chipforge.io/api-reference/endpoint/submit
WEBHOOK /plant/webhook
/submit
Upload hardware design with cryptographic authentication
# Test Cases
Source: https://docs.chipforge.io/api-reference/endpoint/test
/testcases/download
Download validator-specific test suites
# Introduction
Source: https://docs.chipforge.io/api-reference/introduction
The platform uses a microservice architecture with separate REST interfaces for miners and validators,designed for fault tolerance and continuous operation.
## REST API Endpoints
View the Miner enpoints here
View the Validator enpoints here
# Database Section
Source: https://docs.chipforge.io/database
The system uses PostgreSQL with five main tables:
* **challenges**\
Challenge metadata, lifecycle state, cryptographic nonces, validator requirements, and submission limits
* **miner\_submissions**\
Submission metadata, file references, multi-bucket storage (miner/ validator/ archive), validation counts, and status tracking
* **validation\_records**\
Individual validator evaluations, detailed score breakdown, evaluation notes, and validator-specific file paths
* **submission\_nonces**\
Cryptographic nonce management with expiration tracking and rate limiting
* **validator\_api\_keys**\
API key lifecycle, usage tracking, audit trails, and activation/revocation history
# Integration
Source: https://docs.chipforge.io/eda
Description of your new file.
The EDA Server provides the computational backbone for design validation through a two-stage evaluation pipeline.
Verification, Analysis & Aggregation
Performance Characteristics of system
The validator interfaces with both EDA Server and Challenge Server
# File Storage System
Source: https://docs.chipforge.io/file-storage
### S3 Integration
The S3 manager handles secure cloud storage for hardware designs:
* **Hierarchical Organization**\
Designs stored with challenge ID, miner hotkey, submission attempt, and score
* **Access Control**\
Time-limited pre-signed URLs for secure downloads
* **Audit Trail**\
Complete logging of storage operations
# Summary
Source: https://docs.chipforge.io/index
The semiconductor industry stands at a critical inflection point. Despite unprecedented demand for specialized silicon, particularly for **Artificial Intelligence (AI) workloads**, the design and manufacturing of chips remains highly centralized. A handful of corporations control the majority of design intellectual property and fabrication capacity. This centralization creates bottlenecks in innovation, increases costs exponentially, and limits access to custom silicon solutions for the vast majority of organizations.
ChipForge (Subnet SN84) emerges as a revolutionary solution to this fundamental challenge. By leveraging the Bittensor network's decentralized intelligence infrastructure, ChipForge transforms semiconductor design from a closed, capital-intensive process into an **open, competitive marketplace of innovation**. Our subnet enables global participation in chip design through a unique combination of challenge-driven development, automated validation, and cryptocurrency-based incentive mechanisms.
A key innovative point is our focus on **Hardware-Software Co-Design**, particularly for **Edge AI accelerators** (Neural Processing Units or NPUs). Designing for the energy, latency, and size constraints of the edge demands a synergistic approach: co-optimizing the specialized hardware (e.g., custom compute blocks and acceleration logic) alongside the software stack (e.g., compilers and runtime environments) that drives it. ChipForge is structured to incentivize this holistic optimization.
The ChipForge ecosystem represents the convergence of three transformative technologies: decentralized networks, artificial intelligence, and open-source hardware. Through our platform, miners compete to design optimal **RISC-V** (an open-source Instruction Set Architecture or ISA) based processors, edge AI accelerators, and specialized compute blocks. Validators ensure design quality through open-source industry-standard **Electronic Design Automation (EDA)** tools like **Verilator** and **OpenLane**. The result is not theoretical models or simulations, but synthesizable **Register Transfer Level (RTL)** designs with verified Power, Performance, and Area (**PPA**) metrics, ready for FPGA deployment and ultimately silicon fabrication.
# Introduction
Source: https://docs.chipforge.io/performance
**Connection Pool Management**
* **Database Connections**\
Async connection pooling
* **Performance & Scalability**\
Automatic cleanup and memory management
**Caching Strategy**
* **Query Optimization**\
Strategic indexing and query planning
* **Real-time Updates**\
Incremental data refresh
**Scalability**
* **Horizontal Scaling**\
Stateless API design
* **Batch Processing**\
Asynchronous task handling
* **Storage Partitioning**\
S3 bucket segmentation
Structured Logging & Error Tracking
# Platform Components
Source: https://docs.chipforge.io/platform-components
* **Challenge Server**\
The central orchestration system managing challenge lifecycles, submission tracking, batch distribution to validators, score aggregation, and S3 storage operations.
* **Chip Design Team**\
Creates hardware challenges representing state-of-the-art circuit design problems with comprehensive test suites containing millions of instructions.
* **EDA Server**\
A FastAPI application built around open-source EDA tools (OpenLane, Verilator) that analyzes design functionality, area, timing, and power consumption.
# Introduction
Source: https://docs.chipforge.io/scoring
The Chipforge Platform evaluates hardware designs using a comprehensive, weighted scoring function. The scoring methodology is **dynamic**, with both the weight distribution for the primary metrics and a minimum functionality threshold defined by the Chip Design Team in a challenge-specific *weights.json* configuration file. This allows the platform to emphasize specific design qualities, such as performance or silicon efficiency, based on the requirements of the current challenge.
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# System Architecture
Source: https://docs.chipforge.io/system-arch
The platform uses a microservice architecture with separate REST interfaces for miners and validators, designed for fault tolerance and continuous operation.
# Introduction
Source: https://docs.chipforge.io/system-workflows
The complete workflow from submission generation to validation and scoring automation.
Understand the complete end-to-end process of submitting hardware designs and tracking scores through the evaluation pipeline.
Learn how submissions are grouped, distributed, and processed efficiently across validator nodes for scalable performance.
Explore the platform’s mechanisms for detecting, reporting, and recovering from failed jobs or interrupted evaluations.
# Batch Distribution Algorithm
Source: https://docs.chipforge.io/system/batch-distribution
* **Batch Creation**\
Groups of up to 8 submissions assembled
* **Exposure Duration**\
Batches available for sufficient evaluation time
* **Multi-Validator Support**\
Same submission evaluated independently by multiple validators
* **Result Aggregation**\
Individual validator scores maintained separately in leaderboard
# Design and Score Submission
Source: https://docs.chipforge.io/system/design-score
1. Design team publishes challenge
2. Miners discover active challenges
3. Miners submit Verilog designs with signatures
4. Challenge Server validates and stores submissions
5. Submissions grouped into batches (up to 8)
6. Batches exposed to validators
7. Validators submit evaluation scores
8. Multi-validator scores aggregated
9. Leaderboard updated
**Design submission flow**
**Score submission flow**
# Detailed Metric Evaluation
Source: https://docs.chipforge.io/system/detailed
## 1. Functionality Score ($F_c$)
This metric measures the design's functional correctness.
* **Test Generation & Golden Reference:** The Chip Design Team creates comprehensive test suites and runs them on the official **RISC-V ISA Simulator (SPIKE)** to generate the "golden output."
* **Design-Under-Test (DUT) Execution:** The same test cases are executed on the miner's design using the EDA Server's **Verilator** tool for simulation.
* **Scoring:** The $F_c$ score is determined by comparing the DUT’s results against SPIKE's golden outputs.
$$
F_c = \frac{N_{correct}}{N_{total}}
$$
Where $N_{correct}$ is the number of instructions that matched the golden result, and $N_{total}$ is the total number of executed instructions.\
$F_c$ is a value between 0 and 1.
***
## 2. Performance Score ($P_c$)
Performance is quantified as **Instructions Per Second (IPS)**, representing the processing throughput.
* **IPC & Max Clock Speed ():** The processor's **Instructions Per Cycle (IPC)** is measured using performance tests. The processor's maximum clock speed, referred to as $F_{max}$ (Max Frequency), is determined through timing analysis using **OpenLane**.
* **Performance (IPS):** The throughput is calculated as:
$$
IPS = IPC \times F_{max}
$$
* **Normalization:** This raw IPS value is then normalized against a defined benchmark IPS to yield the *0–1* $P_c$ score (a higher IPS results in a score closer to 1).
# Dynamic Scoring Formula
Source: https://docs.chipforge.io/system/dynamic-scoring
The individual weights ($W_{Func}$, $W_{Delay}$, $W_{Area}$) and the minimum Functionality Threshold ($Threshold_{Func}$) are loaded from the `weights.json` file.
* **Constraint:** The submission must achieve a minimum Functionality Score ($F_c$) greater than or equal to the dynamic $Threshold_{Func}$ to receive a non-zero overall score.
$$
\text{IF } F_c \ge Threshold_{Func} :
$$
$$
O_c = \frac{(W_{Func} \cdot F_c) + (W_{Area} \cdot Area) + (W_{Perf} \cdot P_c)}{Total\_W}
$$
$$
\text{IF } F_c < Threshold_{Func} :
$$
$$
O_c = 0
$$
The power metric is not currently evaluated, as it will be integrated for future challenges, such as the Neural Processing Unit (NPU) development, where power is a critical concern.
# Error Recovery
Source: https://docs.chipforge.io/system/error
* **Connection Failures**\
Automatic batch redistribution and status reset
* **Evaluation Errors**\
Graceful degradation with retry mechanisms
# Evaluation Pipeline
Source: https://docs.chipforge.io/system/evaluation
**Stage 1 - Functional Verification**
* Simulates Verilog design against test vectors
* Uses Verilator for verification
* Validates functional correctness
* Generates functionality score
**Stage 2 - Physical Analysis**
* Synthesizes design using Yosys/OpenLane
* Calculates silicon area utilization
* Determines maximum operating frequency
* Estimates power consumption
* Generates area, delay, and power scores
**Score Aggregation**\
Combines metrics into overall score using weighted formula
# Introduction
Source: https://docs.chipforge.io/system/index
The Chipforge Platform coordinates distributed hardware design evaluation across a decentralized network. Miners submit hardware designs in response to challenges, while validators independently assess these submissions using industry-standard EDA tools.
## Technical Documentation
Explore the core modules that make up the challenge platform, including the miner and validator systems.
Understand how different services—frontend, backend, and EDA servers—interact within the challenge ecosystem.
Learn how data such as submissions, scores, and challenge metadata are structured and stored.
Discover how design files, logs, and test outputs are managed, stored, and accessed securely.
Trace the complete workflow from submission generation to validation and scoring automation.
See how the platform integrates with EDA tools like Verilator and OpenLane for hardware simulation and synthesis.
Review the scoring formulas for functionality, performance, and area to understand evaluation metrics.
Explore system optimizations ensuring scalable evaluations and efficient resource usage.
# Monitoring & Observability
Source: https://docs.chipforge.io/system/monitoring
* **Structured Logging**\
Comprehensive audit trails with process tracking
* **Error Tracking**\
Detailed exception reporting
# Performance Characteristics
Source: https://docs.chipforge.io/system/performance
* **Parallel Processing**\
8 concurrent evaluation requests
* **Resource Requirements**\
8 vCPU, 16GB RAM
* **Throughput**\
Minutes per complete evaluation
# Score Normalization
Source: https://docs.chipforge.io/system/score-method
All individual metric scores and the final **Overall Score** (Fc) are normalized to the **0-1 range**, where a score of 1 represents 100% of the ideal metric performance.
| **Metric** | **Score Abbreviation** | **Description** |
| :---------------- | :--------------------- | :----------------------------------------------------- |
| **Functionality** | Fc | Correct execution of the instruction set. |
| **Performance** | Pc | Instructions executed per second (throughput). |
| **Area** | *Area* | Efficiency of silicon utilization (smaller is better). |
| **Power** | N/A (TBD) | Power consumption in milliwatts. |
# Security Features
Source: https://docs.chipforge.io/system/security
**Authentication System**
* **Cryptographic Signatures**\
Ed25519 signature verification (Bittensor compatible)
* **Blockchain Integration**\
Hotkey registration validation
* **Role Verification**\
Distinguishes miners from validators
* **Rate Limiting**\
Throttling on sensitive endpoints
* **Replay Prevention**\
Nonce-based request validation
* **Unique Submission IDs**\
Prevents duplicate processing
**Access Control**
* **API Key Management**\
Secure validator authentication
* **File Access**\
Time-limited S3 URLs
* **Admin Functions**\
Password-protected operations
# Validator Integration
Source: https://docs.chipforge.io/system/validator
The validator interfaces with both EDA Server and Challenge Server:
1. Receives evaluation metrics from EDA Server
2. Submits scores to Challenge Server
3. Identifies top-performing submissions
4. Updates blockchain weights based on performance
# To Conclude
Source: https://docs.chipforge.io/whitepaper/conclusion
ChipForge represents a fundamental paradigm shift in semiconductor design, transforming a centralized, capital-intensive industry into a decentralized, merit-based marketplace. By combining the Bittensor network's incentive mechanisms with cutting-edge EDA tools and open-source hardware principles, we create unprecedented opportunities for innovation in silicon design.\
\
The implications extend far beyond cost reduction or efficiency gains. ChipForge enables a future where custom silicon is accessible to any organization, where edge devices can be optimized for specific applications, and where the pace of hardware innovation matches that of software. As AI workloads continue to proliferate and edge computing becomes ubiquitous, the need for specialized, efficient processors will only intensify.\
\
Our early achievements demonstrate the viability of this approach. The successful development of RISC-V processors through competitive challenges validates our core hypothesis: that decentralized design can match or exceed the quality of traditional approaches while dramatically reducing costs and timelines. As we expand into AI accelerators and advanced architectures, we invite the global community to participate in this revolution.
The path forward is clear. Through ChipForge, we will:
* Democratize access to semiconductor design
* Accelerate innovation through parallel development
* Create open-source hardware ecosystems
* Enable truly decentralized AI infrastructure
Join us in building the future of silicon. The age of decentralized hardware has begun.
# Cost Structure Analysis
Source: https://docs.chipforge.io/whitepaper/economic/analysis
Traditional chip development costs:
* • Design Team: \$5-10 million annually
* • EDA Tools: \$1-2 million annually
* • Prototype Fabrication: \$2-5 million
* • Total Project Cost: \$15-30 million
ChipForge alternative:
* • Challenge Rewards: \$50,000-500,000
* • Validation Costs: \$10,000-50,000
* • Integration Effort: \$100,000-500,000
* • Total Project Cost: \$200,000-1 million
This 10-30x cost reduction democratizes access to custom silicon, enabling new applications and business models previously impossible.
# Network Effects & Value Creation
Source: https://docs.chipforge.io/whitepaper/economic/creation
ChipForge exhibits strong network effects:
Value = k × (Miners × Validators × Challenges)^α\
\
Where:
k = Utility constant
α > 1 (super-linear growth)
As the network grows:
* • More miners → Better designs → More challenges
* • More validators → Faster evaluation → Higher throughput
* • More challenges → Greater rewards → More participation
# Introduction
Source: https://docs.chipforge.io/whitepaper/economic/index
The semiconductor design tools and IP market represents a \$50+ billion annual opportunity growing at 12% CAGR
Traditional chip development costs
ChipForge exhibits strong network effects
# Total Addressable Market
Source: https://docs.chipforge.io/whitepaper/economic/market
The semiconductor design tools and IP market represents a \$50+ billion annual opportunity growing at 12% CAGR. Within this:
* • Edge AI Chips: \$15 billion by 2027
* • Custom ASICs: \$8 billion current market
* • Design Services: \$12 billion annually
ChipForge targets the intersection of these markets, focusing on customers requiring custom silicon but lacking resources for traditional development approaches.
# The Iterative
Source: https://docs.chipforge.io/whitepaper/framework
Hardware Development Framework
ChipForge employs a rigorous, two-phased **Challenge Decomposition Framework** designed to break down the daunting complexity of advanced semiconductor development into manageable, competitive sprints. This approach ensures not only functional correctness but also continuous, market-driven performance optimization.
The process begins with **Sequential Extension Integration**, where the network collaboratively builds the core architecture. Development is layered sequentially based on the **RISC-V Instruction Set Architecture (ISA)**, with the winning, verified Intellectual Property (IP) from one challenge immediately becoming the mandatory base for the next. For instance, the creation of a secure Edge AI processor begins by establishing the base **RV32I core**, which then progresses to integrating extensions like **RV32C** (for code density) and **RV32M** (for arithmetic capability), culminating in the integration of specialized **RV32K Cryptography extensions** for security.
Once a functionally complete design is achieved (e.g., a 100% correct RV32IMCK core), the platform transitions to **Continuous Optimization**. Here, the competition shifts its focus entirely to refining the chip's performance metrics. New challenges are issued against the verified IP, requiring miners to reduce **Area**, increase **Performance**, or lower **Power** consumption—the core PPA metrics. These optimization objectives are strictly defined and weighted via a digital configuration file (weights.json), allowing the ChipForge community to prioritize specific improvements based on real-time market needs (e.g., heavily weighting for ultra-low power consumption for a new IoT device).
Every challenge, whether for functional integration or optimization, is governed by a **comprehensive specification** detailing exact Functional Requirements, mandatory **PPA Targets**, required silicon **Technology Node**, and the objective Validation Criteria, ensuring transparency and reproducibility throughout the entire hardware development lifecycle.
# Alignment and Integrity
Source: https://docs.chipforge.io/whitepaper/incentive/game
Game-Theoretic Alignment and Integrity.
This competitive structure guarantees that competition translates directly into collective progress:
* **Convergence to Optimality:** The strict PPA+F scoring mechanism, paired with the mandatory improvement rule, guarantees that design submissions are continuously driven toward **Pareto-optimal solutions**—the ideal balance of performance, area, and power for the specified function.
* **Integrity Enforcement:** Validator integrity is protected through the Bittensor network's inherent **Slashing Mechanisms** and a system of **Reputation and Stake**, which rewards accurate scoring and financially penalizes non-compliance. Sybil resistance is maintained through the significant computational cost required to execute the required EDA toolchains for functional verification.
# Introduction
Source: https://docs.chipforge.io/whitepaper/incentive/index
The ChipForge economic model is built on the robust, competitive framework of the Bittensor network, strategically designed to align all participant incentives—Miners, Validators, and Challenge Creators—with the core objective: the rapid production of high-quality, verified open-source hardware IP.
The Continuous Optimization Loop (Winner-Takes-All Emissions)
This competitive structure guarantees that competition translates directly into collective progress
# Optimization Loop
Source: https://docs.chipforge.io/whitepaper/incentive/loop
The Continuous Optimization Loop (Winner-Takes-All Emissions)
The platform utilizes a **Winner-Takes-All** reward structure that is applied continuously, ensuring constant effort and iterative improvement within the network:
* **Real-Time Emission:** Unlike traditional contests, rewards (TAO emissions) are not paid at a single endpoint. Instead, emissions are **granted in real-time** to the Miner whose design currently holds the highest verified PPA+F score above the challenge's threshold.
* **Instantaneous Competition:** If a second Miner submits an objectively better design (a higher PPA+F score), the emission stream **immediately switches** to that new winning Miner. This mechanism financially incentivizes a relentless pursuit of optimization, as the reward stream follows the globally best design at all times.
* **Mandatory Improvement Rule:** To ensure a stable but continuously advancing design, a Miner who wins the emission is guaranteed that reward for a minimum of 48 hours, provided their score remains the highest. **However, after that 48-hour period, the current winning Miner must submit an even higher-scoring solution than their previous best to remain eligible for the emission stream.** This rule explicitly enforces constant improvement and discourages complacency, continually pushing the performance frontier of the verified IP.
# Introduction
Source: https://docs.chipforge.io/whitepaper/intro
The Decentralization Imperative
The promise of decentralized artificial intelligence is fundamentally constrained by centralized hardware. While blockchain networks and distributed computing platforms have democratized access to computational resources, the underlying **specialized silicon** that powers these systems remains controlled by a small oligopoly of design houses and foundries. This centralization creates a critical **bottleneck**, undermining the scalability and long-term security of truly decentralized AI infrastructure.
Consider the current state of AI computation: high-performance models require specialized accelerators, **edge devices demand power-efficient inference engines**, and emerging applications in robotics, autonomous vehicles, and IoT necessitate custom silicon solutions. The current path from concept to silicon typically requires **millions of dollars in investment**, years of development time, and access to proprietary Electronic Design Automation (EDA) tools and processes that remain out of reach for most innovators. This asymmetry severely limits the pace of innovation in hardware tailored for decentralized applications.
ChipForge addresses this fundamental market asymmetry by creating the world's first decentralized semiconductor design ecosystem. Our approach transforms hardware development from a sequential, capital-intensive process into a **parallel, incentivized competition** where optimal designs emerge through verifiable market mechanisms rather than corporate hierarchies.
The implications of democratizing access to chip design are significant and extend beyond simple cost reduction. By leveraging global talent and the competitive mechanisms of the Bittensor network, ChipForge enables:
* **Innovation Acceleration:** Enabling the parallel exploration of vast design spaces that would be prohibitively expensive or time-consuming for traditional single-entity approaches.
* **Global Talent Utilization:** Leveraging expertise from engineers worldwide, agnostic to geographic or institutional constraints.
* **Open Hardware Evolution:** Creating a shared digital commons of verified, manufacturable designs that can be freely adapted and continuously improved.
* **Supply Chain Resilience:** Mitigating business risk and reducing dependence on single points of failure in the highly concentrated semiconductor supply chain.
# Detailed Metric Evaluation
Source: https://docs.chipforge.io/whitepaper/methodology/detailed
### 1. Functionality Score ((F\_c))
This metric measures the design's functional correctness.
* **Test Generation & Golden Reference:** The Chip Design Team creates comprehensive test suites and runs them on the official **RISC-V ISA Simulator (SPIKE)** to generate the "golden output."
* **Design-Under-Test (DUT) Execution:** The same test cases are executed on the miner's design using the EDA Server's **Verilator** tool for simulation.
* **Scoring:** The (F\_c) score is determined by comparing the DUT’s results against SPIKE's golden outputs.
$$
F_c = \frac{N_{correct}}{N_{total}}
$$
Where\
(N\_correct) is the number of instructions that matched the golden result, and\
(N\_total) is the total number of executed instructions.\
(F\_c) is a value between 0 and 1.
### 2. Performance Score ((P\_c))
Performance is quantified as **Instructions Per Second (IPS)**, representing the processing throughput.
* **IPC & Max Clock Speed ((F\_))**: The processor's **Instructions Per Cycle (IPC)** is measured using performance tests. The processor's maximum clock speed, referred to as (F\_max) (Max Frequency), is determined through timing analysis using **OpenLane**.
* **Performance (IPS):** The throughput is calculated as:
$$
IPS = IPC \times F_{max}
$$
* **Normalization:** This raw IPS value is then normalized against a defined benchmark IPS to yield the 0–1 (P\_c) score (a higher IPS results in a score closer to 1).
### 3. Area Score ($Area$)
The $Area$ score measures the silicon efficiency of the design.
* **Synthesis & Measurement:** The design is synthesized using **OpenLane (Yosys)** targeting the sky130nm PDK, and the total silicon area is extracted.
* **Normalization:** The $Area$ score is **inversely proportional** to the measured area (a smaller area yields a score closer to 1). This score is normalized against a target area defined by the challenge.
### 4. Power Consumption Score (TBD)
This metric is currently under development. Once integrated, the $Score_{Power}$ will be **inversely proportional** to the measured power consumption, normalized against a target power consumption.
# Dynamic Scoring Formula
Source: https://docs.chipforge.io/whitepaper/methodology/dynamic
The individual weights ($W_{Func}$, $W_{Delay}$, $W_{Area}$) and the minimum Functionality Threshold ($Threshold_{Func}$) are loaded from the `weights.json` file.
* **Constraint:** The submission must achieve a minimum Functionality Score ($F_c$) greater than or equal to the dynamic $Threshold_{Func}$ to receive a non-zero overall score.
$$
\text{IF } F_c \ge Threshold_{Func} :
$$
$$
O_c = \frac{(W_{Func} \cdot F_c) + (W_{Area} \cdot Area) + (W_{Perf} \cdot P_c)}{Total\_W}
$$
$$
\text{IF } F_c < Threshold_{Func} :
$$
$$
O_c = 0
$$
*Note:* The power metric is not currently evaluated, as it will be integrated for future challenges, such as the Neural Processing Unit (NPU) development specifically for edge AI applications, where power is a critical concern.
***
# Introduction
Source: https://docs.chipforge.io/whitepaper/methodology/index
The Chipforge Platform evaluates hardware designs using a comprehensive, weighted scoring function. The scoring methodology is **dynamic**, with both the weight distribution for the primary metrics and a minimum functionality threshold defined by the Chip Design Team in a challenge-specific `weights.json` configuration file. This allows the platform to emphasize specific design qualities, such as performance or silicon efficiency, based on the requirements of the current challenge.
All individual metric scores and the final Overall Score...
The individual weights of Dynamic Scoring Formula
Detailed Metric Evaluation
# Score Normalization
Source: https://docs.chipforge.io/whitepaper/methodology/normal
All individual metric scores and the final **Overall Score** ($O_c$) are normalized to the **0–1 range**, where a score of 1 represents 100% of the ideal metric performance.
| Metric | Score Abbreviation | Description |
| ------------- | ------------------ | ------------------------------------------------------ |
| Functionality | $F_c$ | Correct execution of the instruction set. |
| Performance | $P_c$ | Instructions executed per second (throughput). |
| Area | $Area$ | Efficiency of silicon utilization (smaller is better). |
| Power | N/A (TBD) | Power consumption in milliwatts. |
***
# The Edge Computing Paradox
Source: https://docs.chipforge.io/whitepaper/problem/edge
As AI workloads increasingly move to the edge, the mismatch between hardware requirements and available solutions becomes acute. Edge devices require:
* **Ultra-Low Latency:** Real-time inference with sub-10ms response times.
* **Power Efficiency:** Operation within strict thermal and battery constraints.
* **Cost Optimization:** Bill-of-materials costs compatible with consumer and industrial products.
* **Privacy Preservation:** On-device processing without cloud dependencies, with **on-device security** (authentication, secure communication) as well.
Current solutions fail to address these requirements holistically. General-purpose processors lack the efficiency for complex AI workloads, while existing AI accelerators are optimized for cloud deployments with unlimited power budgets. The result is a **massive unserved market for edge-optimized silicon**.
# Silicon's Centralization Crisis
Source: https://docs.chipforge.io/whitepaper/problem/index
The semiconductor industry exhibits extreme concentration across multiple dimensions
As AI workloads increasingly move to the edge, the mismatch between hardware requirements and available solutions becomes acute.
Traditional chip design follows a waterfall model where verification consumes 60-70% of development time and resources.
# The Monopolization of Innovation
Source: https://docs.chipforge.io/whitepaper/problem/monoply
The semiconductor industry exhibits extreme concentration across multiple dimensions:
Design Intellectual Property: Five companies control over 80% of critical IP blocks used in modern chip designs. This concentration creates artificial scarcity and inflates licensing costs, with some IP blocks costing millions of dollars to license for a single project.
EDA Tools: Three corporations dominate the EDA tool market, with annual licenses exceeding \$1 million for comprehensive toolchains. This creates an insurmountable barrier to entry for independent designers and small teams.
Fabrication Access: Advanced node fabrication (7nm and below) is concentrated in just three companies globally, with minimum order quantities often exceeding \$10 million.
Talent Concentration: The top 20 semiconductor companies employ the vast majority of experienced chip designers, creating a self-reinforcing cycle of centralization.
# The Verification Bottleneck
Source: https://docs.chipforge.io/whitepaper/problem/verification
Traditional chip design follows a waterfall model where verification consumes **60-70% of development time and resources**. A single design iteration can take months, with each bug discovered late in the process potentially adding weeks to the schedule. This sequential approach:
* Limits design space exploration to conservative, incremental improvements.
* Prevents rapid iteration based on real-world feedback.
* Creates enormous financial risk, as errors discovered post-fabrication can cost millions to rectify.
**ChipForge Solution:** To fundamentally disrupt this bottleneck, we are developing a decentralized mechanism where miners are incentivized to **prove a design wrong by finding a bug**, analogous to how miners compete in a blockchain's Proof-of-Work system. This feature, which will function as a specialized subnet for verification challenges, is currently in development and will allow for parallel, competitive verification using open-source EDA tools. Our current focus remains on democratizing the initial design phase.
# Introduction
Source: https://docs.chipforge.io/whitepaper/progress/index
ChipForge has successfully moved beyond the conceptual stage, establishing a production-ready decentralized hardware design platform and achieving significant architectural milestones through the network's initial challenges. Our focus has been on building a robust infrastructure and securing foundational, high-value RISC-V Intellectual Property (IP).
We have established the technical bedrock necessary for distributed hardware design competition and verification
Through successful completion of the Sequential Extension Integration phase, the network has secured a robust, verifiable RISC-V core
# Foundational Infrastructure Achievements
Source: https://docs.chipforge.io/whitepaper/progress/infra
We have established the technical bedrock necessary for distributed hardware design competition and verification:
* **Decentralized Challenge Infrastructure:** Deployed a production-ready platform supporting the continuous optimization loop (Section 7), concurrent challenge execution, cryptographic authentication for all submissions, and automated TAO reward distribution.
* **Integrated EDA Server Pipeline:** Established a comprehensive and reproducible validation pipeline by setting up **containerized EDA Servers** using Docker images for miners and validators. This infrastructure integrates industry-standard open-source tools—**Verilator** (for cycle-accurate simulation), **Yosys** (for synthesis), and **OpenLane** (for physical implementation)—ensuring objective, standardized verification and scoring for all designs.
# RISC-V Architectural IP Secured
Source: https://docs.chipforge.io/whitepaper/progress/risc
Through successful completion of the **Sequential Extension Integration** phase, the network has secured a robust, verifiable RISC-V core:
* **Complete RV32IMCK Core:** Successfully designed and fully validated a 32-bit RISC-V processor that cumulatively integrates the most critical extensions:
* **RV32I (Base Integer):** Core instruction set compliance.
* **RV32M (Multiply/Divide):** High-speed arithmetic unit integration.
* **RV32C (Compressed):** Implementation of compressed instructions for code density.
* **RV32K (Cryptography):** Full integration of the most critical cryptography extensions, including **AES encryption/decryption**, **SHA hashing**, and related bit-manipulation functions.
* **Performance Benchmark:** The verified IP has demonstrated strong initial performance metrics, achieving **Full ISA compliance** with rigorous RISC-V specifications with basic max clock (without any timing optimization) 120MHz and SKY130nm. Closing this same design with a better smaller \*\*node \*\*like tsmc 22-28nm will definately give a clock close to 1GHz.
# Processors to AI Accelerators
Source: https://docs.chipforge.io/whitepaper/roadmap/index
This section details the structured, four-phase development plan for the SN84 Subnet, focusing on the progression from foundational processor development to advanced Edge AI System-on-Chip (SoC) realization. The roadmap incorporates decentralized development via the Bittensor framework to accelerate technical milestones.
RISC-V Core Finalization (Target: Mid-November)
NPU Development (Target: By February 2026)
RTOS Integration and Verification (Target: By Feb 2026)
System-on-Chip Integration (Target: Post-Feb 2026)
Tape-out and Fabrication Readiness (Target: November 2026)
# Phase 1
Source: https://docs.chipforge.io/whitepaper/roadmap/ph1
RISC-V Core Finalization (Target: Mid-November)
The project commences with the definitive establishment of the core processing unit. The objective is the complete specification and finalization of the **RV32IMCK IP core**. This foundational element will incorporate the standard RISC-V RV32 instruction set, augmented by the Integer (I), Multiply/Divide (M), Compressed (C), and essential Cryptography (K) extensions. Completion of this phase delivers the verified hardware foundation necessary for all subsequent integration and software efforts.
# Phase 2
Source: https://docs.chipforge.io/whitepaper/roadmap/ph2
NPU Development (Target: By February 2026)
Following core finalization, development transitions to the specialized Neural Processing Unit (NPU). This phase utilizes the **Google Coral NPU architecture as a verified baseline**. The core activity is the technical benchmarking and optimization of the architecture to achieve superior **PPA (Power, Performance, Area) metrics**. A primary technical focus involves custom optimization of the NPU's Matrix Execution Unit to enhance performance for deep learning workloads, ensuring alignment with emerging RISC-V matrix extension standards.
# Phase 3
Source: https://docs.chipforge.io/whitepaper/roadmap/ph3
RTOS Integration and Verification (Target: By Feb 2026)
This phase is executed **concurrently** with NPU development to optimize the overall schedule. The objective is to achieve reliable software enablement via **RTOS support** (e.g., FreeRTOS or Zephyr) on the finalized RV32IMCK core.
# Phase 4
Source: https://docs.chipforge.io/whitepaper/roadmap/ph4
System-on-Chip Integration (Target: Post-Feb 2026)
Phase 4 constitutes the critical system assembly and verification stage, dependent upon the successful, independent completion of both NPU optimization and RTOS enablement. This phase integrates all primary components into the final SoC architecture:
* The **Main Core** (RV32IMCK with validated RTOS).
* The **Optimized NPU**.
* Essential **OpenCores Peripherals** (including communication interfaces such as I2C, SPI, UART, and Ethernet).
The primary engineering challenge is the unified implementation and verification of an on-chip interconnect standard (such as AXI or Wishbone) to guarantee high-throughput and reliable data flow between all intellectual property (IP) blocks.
# Phase 5
Source: https://docs.chipforge.io/whitepaper/roadmap/ph5
Tape-out and Fabrication Readiness (Target: November 2026)
The final phase is dedicated to transitioning the design to manufacturing. This involves comprehensive, final design verification and quality assurance checks across the entire integrated SoC. Successful completion culminates in the submission of the final, verified **GDSII** file for the fabrication process, marking the conclusion of the core design and development cycle.
# Architectural Philosophy
Source: https://docs.chipforge.io/whitepaper/solution/arch
ChipForge reimagines semiconductor design as a decentralized, competitive marketplace. Our architecture comprises three fundamental components:
Challenge Server: The orchestration layer that manages design challenges, distributes specifications, collects submissions, and coordinates validation. Built on enterprise-grade infrastructure with FastAPI, PostgreSQL, and AWS S3, the Challenge Server ensures reliable, scalable operation while maintaining cryptographic security for all transactions.
Miner Network: A global pool of hardware designers, ranging from individual engineers to AI-powered design automation systems. Miners compete to create optimal solutions for each challenge, leveraging both human creativity and machine intelligence. The competitive dynamic ensures continuous innovation while the cryptocurrency incentives attract top talent globally.
Validator Ecosystem: Independent nodes running standardized EDA tool chains to evaluate designs objectively. Validators execute functional verification, synthesis, and physical implementation to generate comprehensive PPA metrics. This distributed validation ensures no single entity can manipulate results while maintaining reproducibility and transparency.
# Challenge-Driven Development
Source: https://docs.chipforge.io/whitepaper/solution/challenge
ChipForge decomposes complex chip designs into modular challenges, utilizing a specific, standards-based framework to guide development—specifically, the **RISC-V Instruction Set Architecture (ISA)**. This approach shifts chip development from a traditional sequential process to a **competitive sprint among multiple miners**.
#### **Key Mechanisms for Accelerated Development:**
Instead of relying on a single team, ChipForge accelerates development through:
* **Competitive Innovation:** **Dozens of miners** simultaneously compete to deliver the best solution for the exact same design challenge (e.g., implementing the RV32I core). This instantaneous, mass parallelization of design exploration guarantees that the winning output is the **globally optimal design** available at that moment.
* **Speed-to-Reward:** Miners are incentivized to submit their solutions as **early as possible** to maximize their claim on the reward pool. This competitive time-pressure pushes product development timelines forward, significantly compressing the traditional time-to-market.
* **Incremental Complexity:** We build a sophisticated processor step-by-step by layering functional ISA extensions. This allows for **continuous improvement** as each challenge iteration establishes a new benchmark for the underlying hardware.
**Future Feature:** The platform will eventually support the launch of **multiple, distinct challenges concurrently** (e.g., a challenge for an RV32I core running alongside a challenge for a specialized Systolic Array Matrix Multiplier). This will enable true **parallel component development** to further slash overall project completion time.
# Decentralized Hardware Design
Source: https://docs.chipforge.io/whitepaper/solution/index
ChipForge reimagines semiconductor design as a decentralized marketplace of miners, validators, and challenge servers.
ChipForge accelerates chip creation through modular, RISC-V–based design challenges powered by global competition.
The competitive element is driven by rewarding miners based on four critical metrics.
# Core Metrics
Source: https://docs.chipforge.io/whitepaper/solution/metrics
PPA + Functionality (PPA+F)
The competitive element is driven by rewarding miners based on four critical metrics, which extend the traditional industry standard of PPA (Power, Performance, Area):
1. **Functionality (F):** The design must function correctly according to the required ISA specification.
2. **Performance (P):** Highest clock speed or operations-per-second.
3. **Power (P):** Minimum power consumption.
4. **Area (A):** Smallest physical silicon footprint.
Miners with the **best overall design** across these four metrics are rewarded. While full functional correctness is the ultimate objective, ChipForge strategically rewards miners based on outstanding work in PPA metrics, even if functionality is not 100% complete at the start. This incentivizes **pioneering hardware optimization** and rapid iterative feedback.
# Challenge Server Architecture
Source: https://docs.chipforge.io/whitepaper/technical/challenge
The Challenge Server implements a sophisticated orchestration system managing the complete lifecycle of design challenges:
API Layer: RESTful endpoints implemented in FastAPI providing separate interfaces for miners and validators. Authentication via Ed25519 signatures ensures cryptographic security while rate limiting prevents abuse.
Database Layer: PostgreSQL database managing challenge metadata and specifications, miner submissions and validation records, cryptographic nonces for replay prevention, and API keys for validator authentication.
Storage Layer: AWS S3 integration providing hierarchical organization of design files, time-limited pre-signed URLs for secure access, complete audit trails of all operations, and multi-region replication for reliability.
Processing Layer: Asynchronous task processing via Celery combined with Redis enabling batch formation for validator distribution, score aggregation from multiple validators, automated challenge lifecycle management, and real-time leaderboard updates.
# Technical Architecture
Source: https://docs.chipforge.io/whitepaper/technical/index
System Overview
The ChipForge platform operates as a distributed system with clearly defined interfaces and responsibilities. The ecosystem integrates external clients (miners and validators), the ChipForge platform (Challenge Server with supporting services), and external services (GitHub, S3, PostgreSQL, and Blockchain).
The Challenge Server implements a sophisticated orchestration system managing the complete lifecycle of design challenges
Miners interact with the ChipForge ecosystem through a well-defined workflow
Validators provide the critical function of objective design evaluation.
# Miner Workflow
Source: https://docs.chipforge.io/whitepaper/technical/miner
Miners interact with the ChipForge ecosystem through a well-defined workflow:
1. Discovery Phase: Query active challenges and download specifications
2. Design Phase: Develop RTL implementations meeting challenge requirements
3. Validation Phase: Local testing using provided testbenches
4. Submission Phase: Upload designs with cryptographic signatures
5. Evaluation Phase: Monitor validation progress and scores
6. Reward Phase: Receive TAO tokens for winning designs
The platform supports both human designers using traditional EDA tools and AI-powered systems generating RTL through large language models. This hybrid approach leverages human creativity for architectural innovations while utilizing AI for optimization and parameter tuning.
# Validator Operations
Source: https://docs.chipforge.io/whitepaper/technical/validator
Validators provide the critical function of objective design evaluation:
Functional Verification: Using Verilator, validators simulate designs against comprehensive test suites containing millions of instructions. Results are compared against golden references to determine functional correctness.
Synthesis Analysis: Employing Yosys and OpenLane, validators synthesize designs to gate-level netlists, extracting accurate area metrics and timing characteristics.
Score Calculation: Combining individual metrics using challenge-specific weights to generate overall scores that reflect the relative importance of different optimization objectives.