> ## Documentation Index
> Fetch the complete documentation index at: https://docs.chipforge.io/llms.txt
> Use this file to discover all available pages before exploring further.

# RISC-V Architectural IP Secured

Through successful completion of the **Sequential Extension Integration** phase, the network has secured a robust, verifiable RISC-V core:

* **Complete RV32IMCK Core:** Successfully designed and fully validated a 32-bit RISC-V processor that cumulatively integrates the most critical extensions:
  * **RV32I (Base Integer):** Core instruction set compliance.
  * **RV32M (Multiply/Divide):** High-speed arithmetic unit integration.
  * **RV32C (Compressed):** Implementation of compressed instructions for code density.
  * **RV32K (Cryptography):** Full integration of the most critical cryptography extensions, including **AES encryption/decryption**, **SHA hashing**, and related bit-manipulation functions.
* **Performance Benchmark:** The verified IP has demonstrated strong initial performance metrics, achieving **Full ISA compliance** with rigorous RISC-V specifications with basic max clock (without any timing optimization) 120MHz and SKY130nm. Closing this same design with a better smaller \*\*node \*\*like tsmc 22-28nm will definately give a clock close to 1GHz.