> ## Documentation Index
> Fetch the complete documentation index at: https://docs.chipforge.io/llms.txt
> Use this file to discover all available pages before exploring further.

# Phase 1

> RISC-V Core Finalization (Target: Mid-November)

The project commences with the definitive establishment of the core processing unit. The objective is the complete specification and finalization of the **RV32IMCK IP core**. This foundational element will incorporate the standard RISC-V RV32 instruction set, augmented by the Integer (I), Multiply/Divide (M), Compressed (C), and essential Cryptography (K) extensions. Completion of this phase delivers the verified hardware foundation necessary for all subsequent integration and software efforts.