> ## Documentation Index
> Fetch the complete documentation index at: https://docs.chipforge.io/llms.txt
> Use this file to discover all available pages before exploring further.

# Phase 4

> System-on-Chip Integration (Target: Post-Feb 2026)

Phase 4 constitutes the critical system assembly and verification stage, dependent upon the successful, independent completion of both NPU optimization and RTOS enablement. This phase integrates all primary components into the final SoC architecture:

* The **Main Core** (RV32IMCK with validated RTOS).
* The **Optimized NPU**.
* Essential **OpenCores Peripherals** (including communication interfaces such as I2C, SPI, UART, and Ethernet).

The primary engineering challenge is the unified implementation and verification of an on-chip interconnect standard (such as AXI or Wishbone) to guarantee high-throughput and reliable data flow between all intellectual property (IP) blocks.