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Stage 1 - Functional Verification
  • Simulates Verilog design against test vectors
  • Uses Verilator for verification
  • Validates functional correctness
  • Generates functionality score
Stage 2 - Physical Analysis
  • Synthesizes design using Yosys/OpenLane
  • Calculates silicon area utilization
  • Determines maximum operating frequency
  • Estimates power consumption
  • Generates area, delay, and power scores
Score Aggregation
Combines metrics into overall score using weighted formula
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