Skip to main content
The semiconductor industry stands at a critical inflection point. Despite unprecedented demand for specialized silicon, particularly for Artificial Intelligence (AI) workloads, the design and manufacturing of chips remains highly centralized. A handful of corporations control the majority of design intellectual property and fabrication capacity. This centralization creates bottlenecks in innovation, increases costs exponentially, and limits access to custom silicon solutions for the vast majority of organizations. ChipForge (Subnet SN84) emerges as a revolutionary solution to this fundamental challenge. By leveraging the Bittensor network’s decentralized intelligence infrastructure, ChipForge transforms semiconductor design from a closed, capital-intensive process into an open, competitive marketplace of innovation. Our subnet enables global participation in chip design through a unique combination of challenge-driven development, automated validation, and cryptocurrency-based incentive mechanisms. A key innovative point is our focus on Hardware-Software Co-Design, particularly for Edge AI accelerators (Neural Processing Units or NPUs). Designing for the energy, latency, and size constraints of the edge demands a synergistic approach: co-optimizing the specialized hardware (e.g., custom compute blocks and acceleration logic) alongside the software stack (e.g., compilers and runtime environments) that drives it. ChipForge is structured to incentivize this holistic optimization. The ChipForge ecosystem represents the convergence of three transformative technologies: decentralized networks, artificial intelligence, and open-source hardware. Through our platform, miners compete to design optimal RISC-V (an open-source Instruction Set Architecture or ISA) based processors, edge AI accelerators, and specialized compute blocks. Validators ensure design quality through open-source industry-standard Electronic Design Automation (EDA) tools like Verilator and OpenLane. The result is not theoretical models or simulations, but synthesizable Register Transfer Level (RTL) designs with verified Power, Performance, and Area (PPA) metrics, ready for FPGA deployment and ultimately silicon fabrication.