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Documentation Index

Fetch the complete documentation index at: https://docs.chipforge.io/llms.txt

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This section details the structured, four-phase development plan for the SN84 Subnet, focusing on the progression from foundational processor development to advanced Edge AI System-on-Chip (SoC) realization. The roadmap incorporates decentralized development via the Bittensor framework to accelerate technical milestones.

Phase 1

RISC-V Core Finalization (Target: Mid-November)

Phase 2

NPU Development (Target: By February 2026)

Phase 3

RTOS Integration and Verification (Target: By Feb 2026)

Phase 4

System-on-Chip Integration (Target: Post-Feb 2026)

Phase 5

Tape-out and Fabrication Readiness (Target: November 2026)