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1. Functionality Score ((F_c))

This metric measures the design’s functional correctness.
  • Test Generation & Golden Reference: The Chip Design Team creates comprehensive test suites and runs them on the official RISC-V ISA Simulator (SPIKE) to generate the “golden output.”
  • Design-Under-Test (DUT) Execution: The same test cases are executed on the miner’s design using the EDA Server’s Verilator tool for simulation.
  • Scoring: The (F_c) score is determined by comparing the DUT’s results against SPIKE’s golden outputs.
Fc=NcorrectNtotalF_c = \frac{N_{correct}}{N_{total}} Where
(N_correct) is the number of instructions that matched the golden result, and
(N_total) is the total number of executed instructions.
(F_c) is a value between 0 and 1.

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2. Performance Score ((P_c))

Performance is quantified as Instructions Per Second (IPS), representing the processing throughput.
  • IPC & Max Clock Speed ((F_)): The processor’s Instructions Per Cycle (IPC) is measured using performance tests. The processor’s maximum clock speed, referred to as (F_max) (Max Frequency), is determined through timing analysis using OpenLane.
  • Performance (IPS): The throughput is calculated as:
IPS=IPC×FmaxIPS = IPC \times F_{max}
  • Normalization: This raw IPS value is then normalized against a defined benchmark IPS to yield the 0–1 (P_c) score (a higher IPS results in a score closer to 1).

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3. Area Score (AreaArea)

The AreaArea score measures the silicon efficiency of the design.
  • Synthesis & Measurement: The design is synthesized using OpenLane (Yosys) targeting the sky130nm PDK, and the total silicon area is extracted.
  • Normalization: The AreaArea score is inversely proportional to the measured area (a smaller area yields a score closer to 1). This score is normalized against a target area defined by the challenge.

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4. Power Consumption Score (TBD)

This metric is currently under development. Once integrated, the ScorePowerScore_{Power} will be inversely proportional to the measured power consumption, normalized against a target power consumption.